This invention relates to a semiconductor integrated circuit device including a logic circuit which requires high reliability, and more particularly to a semiconductor integrated circuit device including a logic circuit which has improved the integration density and/or operation speed without sacrificing the reliability.
For improving the reliability of the logic circuit, ISSCC DIGEST OF TECHNICAL PAPERS, pp. 54-55; Feb., 1982 (IEEE) proposed a method in which a parity bit is added to each data to enable detection of the data error, while the logic circuit is doubled and their outputs are compared to detect the error in the logic operation.
FIG. 1 illustrates an example of the error detection in this prior art. The arithmetic logic unit (ALU) is doubled to detect the error. ALU1 and ALU2 have logically completely the same function. Data A and B are inputted to both the ALU1 and the ALU2. The operation result of the ALU1 is outputted at an output terminal F. At the same time, the operation results of the ALU1 and ALU2 are supplied to a comparison circuit CMP to check the existence or absence of the error of the operation actions. The comparison circuit CMP generates the error detection signal at a terminal E. Regarding the error detection of the input data, the parity bits P.sub.A and P.sub.B associated with the data A and B are inputted and checked in parity check circuits PCA and PCB, the result of which are outputted at output terminals E.sub.A and E.sub.B. Further, a parity generation circuit PG calculates a parity output based on the ALU output and supplies the parity output at an output terminal P.sub.F.
FIG. 2 illustrates an example in which the above-mentioned prior art is applied to an operation unit comprising ALU's, registers, pre-shifters, etc. The construction of an ALU unit 16 is practically the same as that of FIG. 1. In the figure, reference symbols DL1601 and DL1602 denote data latches, PL16 a parity latch, R1501 and R1502 registers, and PS1501 and P.sub.A 1502 pre-shifters. In this example, the parity check of the register outputs is carried out in parity check circuits PCA and PCB. The results of the parity check are supplied from respective terminals E.sub.A and E.sub.B. The operation results of two sets of the doubled pre-shifters PS1501 and PS1502 (shift circuits SH1501 and SH1502 and shift circuits SH1503 and SH1504) are respectively compared and checked in comparison circuits CMP1601 and CMP1602. The results of the comparison and check are outputted from terminals E1601 and E1602.
By employing such construction as described above, it is made possible (1) to detect the error of the input data using the parity bit, (2) to detect the error of the operation result by the doubled structure of the ALU and the pre-shifter, and (3) to add a parity bit to the operation results of the ALU.
FIG. 3 illustrates an example of a combination of a comparison and check circuit for the operation results of doubled circuits and a diagnosis circuit for this comparison and check circuit. In the figure, reference symbols 1301 and 1302 denote doubled operation circuits having the same function, EOR13 an exclusive OR (EOR) circuit for comparison and check, 1303 a diagnosis circuit for the EOR circuit, and AND1301 and AND1302 ADD circuits. The doubled operation circuits 1301 and 1302 generate the same operation results as far as they work normally. The comparison and check circuit EOR13 cannot discriminate whether the operation circuits 1301 and 1302 work normally or the outputs thereof are accidentally fixed at normal values. Therefore, the output of one operation circuit is forced to take a different value from the output of the other operation circuit by a diagnosis circuit 1303 formed, in this example, of the AND circuits AND1301 and AND1302, and the comparison and check circuit EOR13 performs diagnosis. Thus, a logic circuit 1300 including an error detection circuit is obtained. In the figure, reference symbols T.sub.2 and T.sub.3 denote diagnosing control signals which are set at the high level in the normal operation. Therefore, signals OUT1301 and OUT1302 are directly inputted to the comparison and check circuit EOR31. When both the logic operation circuits 1301 and 1302 work normally, the signals OUT1301 and OUT1302 take the same value. Therefore, the output ER13 of the comparison and check circuit EOR13 always takes the low level. Then, discrimination cannot be made between the normal operation of the comparison and check circuit EOR13 and the case in which the output in pinned at the low level by some malfunction. For enabling discrimination of these two in the diagnosis of the logic circuit, such inputs are applied to A11-D11 that for example when the control signal T.sub.2 is set to the low level the output of the AND circuit AND1301 becomes the low level and the signal OUT1301 at this moment becomes of the high level. When the comparison and check circuit EOR13 operates normally, the output ER13 becomes the high level. When there is a malfunction, the output ER13 becomes the low level. In this way, diagnosis of the comparison and check circuit EOR13 can be made by bringing one of the diagnosis control signal T.sub.2 or T.sub.3 to the low level.
The logic circuits having error detection ability as explained in connection with FIGS. 1 to 3 have following problems.
First, regarding the delay time of the ALU unit, since the parity generation operation is performed after the completion of the operation of the ALU unit using the result of the operation, the delay time becomes the sum of the two operations and hence increases compared to the case when the parity bit is not added. This increment amounts to e.g. about 20% of the total delay time in the 32 bits ALU and forms a factor of disturbing the improvement in the operation speed. Also, by providing a diagnosing circuit for the comparison and check circuit, the delay time of the error detection signal increases.
Next, regarding the lay-out area, each one additional circuit is required for the check of the result in addition to the one for operation with respect to the ALU which has a large logic scale and requires a wide area and with respect to the pre-shifter which has many wiring lines and requires a wide area. Further, since a parity check circuit for the register output, a comparison and check circuit for the ALU output and the pre-shifter output, and a diagnosing circuit for the comparison and check circuit are required, the occupation area should increase.
Further, for improving the operation speed in the prior art, there are such ways as reduction of the delay times of the respective stages of the circuit by the improvement of the driving ability of the active elements such as transistor constituting the logic circuit, a reduction of the number of circuit stages in the critical path by the improvement in the degree of logic parallelism. The former requires to increase the area of the active elements and the latter requires to increase the number of circuits. Either of them leads to an increase in the lay-out area. Therefore, when improvement in the operation speed is attempted in an operation unit utilizing the prior art which requires a large lay-out area for the error detection through doubled circuit construction, there is a possibility that the high integration of the LSI should remarkably be disturbed.